1. Field of the Invention
The present invention generally relates to communication systems. More particularly, the invention generally relates to lower latency decoding techniques usable in communication systems.
2. Background Information
In general, communication systems permit information to be transmitted from a source to a destination. An issue that is addressed in various communication systems is how to detect errors that may occur in the transmitted information. For example, a bit may be transmitted as a logic 1, but be received as a logic 0, and vice versa. To address such errors in many types of communication systems, the transmitting device may include logic that codes the information to be sent to the destination device. The destination device may include decode logic that decodes the coded information to recreate the original information.
Numerous types of coding schemes exist. In general, a coding scheme causes redundant bits of information (e.g., parity bits) to be included with the data bits to form a xe2x80x9ccode word.xe2x80x9d The redundant bits permit the decoding logic to detect whether any of the data bits were received in error and to correct any bits received in error. Generally, longer code words are desirable to achieve higher efficiency, but disadvantageously take a longer time to decode than shorter code words. By contrast, shorter codes advantageously can be decoded faster than longer code words, but are less efficient than longer code words (i.e. may require more redundant bits per set of data bits). Coding schemes may be characterized by a xe2x80x9ccoding ratexe2x80x9d which refers to the portion of the total number of bits in a packet or code word that comprise data bits (as opposed to redundant/parity bits). As such, more redundant bits per set of data bits may be required to achieve similar reliabilities for decoded bits. By way of additional terminology, the xe2x80x9cerror ratexe2x80x9d refers to the number of bits in error received as a percentage of the total bits transmitted.
By way of an example, turbo codes generally comprise a large class of iterative near-channel-capacity error correction codes. By their nature, turbo codes are relatively compute-intensive and suffers from longer latency than other coding schemes. As used herein, latency refers to the time interval from the point when a codeword has been received in its entirety to the time at which the entire codeword has been decoded and all of the recovered data bits are available for further use. Turbo codes, however, permits a desired error rate to be achieved with a higher coding rate than other types of coding schemes. Thus, turbo codes may suffer from higher latency, but may also be characterized by higher efficiency than other coding schemes.
The longer latency of coding schemes like turbo codes may be acceptable for some applications, but not others. At least some wireless networks (e.g., networks compliant with the IEEE 802.11 standard) require a packet to be acknowledged within a prescribed amount of time. This means that the receiving device must decode the packet fast enough to be able transmit back an acknowledgment within the time prescribed by the applicable wireless standard. The relatively long latency typical of turbo codes makes it difficult to implement turbo codes in a network that requires relatively fast decoding. Faster decoding schemes may be needed, but such schemes may be undesirably inefficient.
The problem described above may be solved by an electronic device that is adapted to receive a packet comprising a plurality of codewords comprising pre-processing logic, a first decoder, and a second decoder. The pre-processing logic causes some of said codewords to be provided to the first decoder and other of said codewords to be provided to the second decoder. The codewords may be of different lengths and/or different code rates. Further, the first and second decoders may implement the same or different decoding technique.